A FinFET is a field effect transistor which has a narrow, active area of a semiconductor material protruding from a substrate so as to resemble a fin. The fin includes source and drain regions, with areas of the fin separated by shallow trench isolation (STI). The FinFET also includes a gate region located between the source and the drain regions. The gate region is formed on a top surface and sidewalls of the fin such that it wraps around the fin. The portion of the fin extending under the gate between the source region and the drain region is the channel region.
FinFETs are regarded as main candidates to replace conventional planar bulk MOSFETs in advanced (beyond 32 nm node) CMOS. This is mainly due to their superior gate control over the channel, resulting in improved short-channel effect immunity and Ion/Ioff ratio.
One type of FinFET is fabricated on silicon on insulator (SOI) wafers, which provides low leakage current from source to drain because there is an oxide layer below the fin which blocks the leakage current. Another type of FinFET is fabricated on conventional bulk silicon wafers. These FinFETs can be considered advantageous due to their lower cost and the option to co-integrate conventional planar bulk FETs and FinFETs in a single product.
The common approach for multi Vt offering is through well doping. In current FinFET processing, however, it is hard to achieve a wide range of threshold voltage solely by well doping in the fins. Moreover, in high-k and metal gate FinFET technology, the gate first integration has become increasingly difficult due to the complexity induced by channel SiGe and NFET and PFET gate stack patterning and RIE (reactive ion etching) processes, with acceptable profile around the fins of the FinFET.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.